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Ordering number : ENA0503
LC72725KM, LC72725KV
Overview
CMOS IC
RDS(RBDS) Demodulation IC
The LC72725KM and LC72725KV are ICs that implement the signal processing required by the European Broadcasting Union RDS (Radio Data System) standard and by the US NRSC (National Radio System Committee) RBDS (Radio Broadcast Data System) standard. These ICs include band-pass filter, demodulator,and data buffer RAM on chip. RDS data can be read out from this on-chip memory by external clock input in slave operation mode.
Functions
* Bandpass filter: Switched capacitor filter (SCF) * RDS Demodulation: 57KHz carrier and RDS data clock regeneration, biphase decode, differential decode. * Buffer RAM: 128 bit (about 100ms) can be restored in the on-chip data buffer RAM. * Data output: Master or slave output mode can be selected. * RDS-ID: Detect RDS signal which can be reset by RST signal input. * Standby control: Crystal oscillator can be stopped. * Fully adjustment free * Low Voltage
Specifications
Absolute Maximum Ratings at Ta = 25C, VSSd = VSSa = 0V
Parameter Maximum supply voltage Maximum input voltage Symbol VDD max VIN1 max VIN2 max Maximum output voltage VO1 max VO2 max VO3 max Maximum output current IO1 max IO2 max Pin Name VDDd, VDDa * TEST, MODE, XIN, RDCL, RST MPXIN, CIN RDS-ID(READY) XOUT, RDDA, RDCL FLOUT XOUT, FLOUT, RDDA, RDCL RDS-ID(READY) Conditions VDDaVDDd+0.3V Ratings -0.3 to +6.5 -0.3 to VDDd+0.3 -0.3 to VDDa+0.3 -0.3 to +6.5 -0.3 to VDDd+0.3 -0.3 to VDDa+0.3 +2.0 +8.0 Unit V V V V V V mA mA
* VDDaVDDd+0.3V
Continued on next page.
Any and all SANYO Semiconductor products described or contained herein do not have specifications that can handle applications that require extremely high levels of reliability, such as life-support systems, aircraft's control systems, or other applications whose failure can be reasonably expected to result in serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest you before usingany SANYO Semiconductor products described or contained herein in such applications. SANYO Semiconductor assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor products described or contained herein.
91306HKIM 20060822-S00002,20060823-S00002 No.A0503-1/9
LC72725KM, 72725KV
Continued from preceding page.
Parameter Allowable power dissipation Symbol Pd max Pin Name Conditions (Ta85C)MFP16 (Ta85C)SSOP16 Operating temperature Topr1 Topr2 Storage temperature Tstg VDD = 2.7V to 5.5V VDD = 3.0V to 5.5V Ratings 140 100 -20 to +70 -40 to +85 -40 to +125 Unit mW mW C C C
Allowable Operating Ranges at Ta = -20 to +70C, VSSd = VSSa = 0V, VDDd = VDDa = 2.7V to 5.5V Ta = -40 to +85C, VSSd = VSSa = 0V, VDDd = VDDa = 3.0V to 5.5V
Parameter Supply voltage Symbol VDD1 VDD2 Input high-level voltage VIH1 VIH2 Input low-level voltage Output voltage VIL VO1 VO2 Input amplitude VIN VXIN Guaranteed crystal oscillator frequencies Crystal oscillator operating range RDCL setup time RDCL high-level time RDCL low-level time Data output time READY output time READY low-level time tCS tCH tCL tDC tRC tRL RDCL, RDDA RDCL RDCL RDCL, RDDA RDCL, READY READY 0 0.75 0.75 0.75 0.75 107 TXtal XIN, XOUT Fo = 4.332MHz Xtal Pin Name VDDd, VDDa VDDd, VDDa TEST, MODE, RST RDCL TEST, MODE, RST, RDCL RDDA, RDCL RDS-ID(READY) MPXIN XIN XIN, XOUT CI120 f = 572kHz 1.6 400 4.332 100 Conditions min Ta = -20 to +70C Ta = -40 to +85C 2.7 3.0 0.7VDDd 0.7VDDd 0 Ratings typ max 5.5 5.5 6.5 VDDd 0.3VDDd VDDd 6.5 50 1500 V V V V V mVrms mVrms MHz ppm s s s s s ms V unit
No.A0503-2/9
LC72725KM, 72725KV
Electrical Characteristics for the Allowable Operating Ranges
Parameter Input resistance Symbol Rmpxin Rcin Internal feedback resistance Center frequency -3dB band width Gain Stop band attenuation fc BW-3dB Gain Att1 Att2 Att3 Reference voltage output Hysteresis Output low-level voltage Vref VHIS VOL1 VOL2 Output high-level voltage Input high-level current VOH IIH1 IIH2 Input low-level current IIL1 IIL2 Output off leakage current Current drain IDD VDDd+VDDa VDDd+VDDa (VDDd = VDDa = 3V) 5 IOFF FLOUT FLOUT MPXIN-FLOUT FLOUT FLOUT FLOUT Vref TEST, MODE, RST, RDCL RDDA, RDCL RDS-ID(READY) RDDA, RDCL TEST, MODE, RST, RDCL XIN TEST, MODE, RST, RDCL XIN RDS-ID(READY) VI = 0V VO = 6.5V 2.0 VI = VDDd VI = 0V 2.0 I = 2mA I = 8mA I = 2mA VI = 6.5V VDDd-0.4 5.0 11 5.0 11 5.0 f = 57kHz f = 7kHz F<45kHz, f>70kHz F<20kHz VDDa = 3V 56.5 2.5 28 30 40 50 1.5 0.1VDDd 0.4 0.4 Rf Pin Name MPXIN-VSSa CIN-VSSa XIN Conditions min f = 57kHz f = 57kHz Ratings typ 100 100 1.0 57.0 3.0 31 57.5 3.5 34 max k k M kHz kHz dB dB dB dB V V V V V A A A A A mA unit
Package Dimensions
unit : mm (typ) 3035B [LC72725KM]
10.0 16 9
Package Dimensions
unit : mm (typ) 3178B [LC72725KV]
5.2 16 9
4.4 6.4
0.63
4.4
(0.56)
1 1.27 0.35
8
(1.5)
1.7max
1 (0.33) 0.65
8 0.22
1.5max
0.15
SANYO : MFP16(225mil)
(1.3)
0.1
SANYO : SSOP16(225mil)
0.1
0.5
0.15
6.4
No.A0503-3/9
LC72725KM, 72725KV
Pin Assignment
XOUT
VSSd
MODE 7 FLOUT
RDCL
VDDd
16 15 14 13 12 11 10
LC72725KM, LC72725KV
1 RDS-ID/READY 2 RDDA 3 VREF 4 MPXIN 5 VDDa 6 VSSa 8 CIN Top view
Block Diagram
+3V VDDa REFERENCE VOLTAGE
VREF
TEST 9
RST
XIN
FLOUT
CIN PLL (57kHz) VREF CLOCK RECOVERY (1187.5Hz) VDDd
+3V
VSSa MPXIN
VSSd
ANTIALIASING FILTER
57kHz BPF (SCF)
SMOOTHING FILTER
DATA DECODER
RDDA RDCL
RAM (128bit) CLK(4.332MHz) TEST TEST OSC RDS-ID DETECT
MODE RST RDS-ID/ READY
XIN
XOUT
No.A0503-4/9
LC72725KM, 72725KV
Pin Descriptions
Pin No. 3 Pin Name VREF I/O Output Function Reference voltage output (Vdda/2) Pin Circuit
VDDa
VSSa
4 MPXIN Input Baseband (multiplexed) signal input
VDDd
VSSd
7 FLOUT Output Subcarrier output (filter output)
8
CIN
Input
Subcarrier input (comparator input)
VDDa
VSSa
5 6 14 13 VDDa VSSa XOUT XIN Output Input Analog system power supply (+3V) Analog system ground Crystal oscillator output (4.332MHz) Crystal oscillator input (external reference signal input)
VREF
VDDd XIN VSSd XOUT
9 10 15 2
TEST MODE RST RDDA Output
Test input Read out mode (0:master, 1:slave) RDS-ID/RAM reset (active high) RDS data output
S VSSd VDDd
VSSd
16 RDCL I/O RDS clock output (master mode) / RDS read out clock input (slave mode)
VDDd
S
1 RDS-ID/ READY Output RDS reliability data output (High:data with high RDS reliability Low: data with low RDS reliability) READY output (active high) 12 11 VDDd VSSd Digital system power supply (+3V) Digital system ground
VSSd
VSSd
No.A0503-5/9
LC72725KM, 72725KV
Input/Output Data Format
TEST 0 0 1 1 MODE 0 1 0 1 Circuit Operation Mode Master read out mode Slave read out mode Standby mode (crystal oscillator stopped) IC test mode which is not available to user applications. RDCL Pin Clock output Clock input RDS-ID/READY Pin RDS-ID output READY output -
RST Pin RST = 0 RST = 1 Normal operation RDS-ID * demodulation circuit clear + READY * memory clear (when slave mode)
RDS-ID/READY Pin Master mode Slave mode RDS-ID output (Active-high) READY output (Active-high)
Note: RDS-ID(READY) pin is an n-channel open-drain output, and requires an external pull-up resistor to output data.
RDCL/RDDA Output Timing in Master Mode
421s RDCL output 421s Tp1
RDDA output 17s Tp21
17s
RDS-ID Output Timing
RDS-ID High/Low High/Low High/Low High/Low High/Low High/Low High/Low
RDCL
RDDA
Note: RDS-ID is High: data with high RDS reliability, Low: data with low RDS reliability
No.A0503-6/9
LC72725KM, 72725KV
RST Operation in Master Mode
Tp3250ns RST RDSdetection circuit output (IC internal) RDCL RDDA
Note: RDCL and RDDA outputs keep high level after input of RST until RDS detection circuit output is detected.
RDCL Operation in Slave Mode
tRH tCS
READY RDCL

tCH
tCL tDC tCS
tRC
RDDA
Pin Name Conditions min 0 0.75 0.75 0.75 0.75 107 Ratings typ max s s s s s ms
Parameter RDCL setup time RDCL high-level time RDCL low-level time Data output time READY output time READY high-level time
Symbol tCS tCH tCL tDC tRC tRH
unit
RDCL,RDDA RDCL RDCL RDCL,RDDA RDCL,READY READY
No.A0503-7/9
LC72725KM, 72725KV
Notes: 1. RDCL input must be started after READY signal goes high. When READY signal is low, RDCL must be low level. 2. READY status must be checked after tRC time from RDCL is set low. If the READY status is high, then next read cycle can be continued. If the READY status is low, next RDCL clock input must be stopped. 3. If the above condition is satisfied, RDS data (RDDA) can be read out at both rising and falling edge of RDCL. 4. READY signal goes low after the last data is read out from on-chip memory. If one RDS data is stored in the memory, READY signal goes high again. 5. When the reception channel is changed, a memory and READY reset must be applied using RST input. If a reset is not applied, reception data from the previous channel may remain in memory. If RST input is applied, reception data is not stored in memory until the first RDS-ID is detected, and READY output goes high after the first RDS-ID is detected. After the first RDS-ID is detected, reception data is stored even if RDS-ID is not detected. 6. The readout mode may be switched between master and slave modes during readout. Applications must observe the following points to assure data continuity during this operation. 1) Data acquisition timing in master made Data must be read on the falling edge of RDCL 2) Timing of the switch from master mode to slave mode After the RDCL output goes low and the RDDA data has been acquired, the application must set MODE high immediately. Then, the microcontroller starts output by setting the RDCL signal low. The microcontroller RDCL output must start within 840s (tms) after RDCL went low. In this case, if the last data read in master mode was data item n, then data starting with item n+1 will be written to memory. 3) Timing of the switch from slave mode to master mode After all data has been read from memory and READY has gone high, the application must then wait until READY goes low once again the next time (timing A in the figure), immediately read out one bit of data and input the RDCL clock. Then, at the point READY goes high, the microcontroller must terminate RDCL output and then set MODE low. The application must switch MODE to low within 840s (tms) after READY goes low (timing A in the figure).
tms
RDCL (microcontroller status) RDCL (IC status) RDCL MODE READY RDDA n INPUT OUTPUT OUTPUT INPUT undefined

INPUT OUTPUT
Timing A
tsm
n-2
n-1
n+1
m
m+1
m+2
No.A0503-8/9
LC72725KM, 72725KV
Sample Application Connection Circuit (for master mode operation)
VDDd 10k RDSID/READY RDDA 10F VSSa MPXIN 330pF VDDa 0.1F 6 VSSa 7 560pF 8 VSSa FLOUT CIN VSSd MODE TEST 11 VSSd 10 9 VSSd 5 +
1 RDSID/READY 2 RDDA 3 4 VREF MPXIN VDDa RDCL RST XOUT XIN VDDd
16 15 14 4.332MHz 13
RDCL RST
22pF 12 VDDd 0.1F VSSd
22pF VSSd
Note: If the RST pin is unused, it must be connected to ground.
Specifications of any and all SANYO Semiconductor products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment. SANYO Semiconductor Co., Ltd. strives to supply high-quality high-reliability products. However, any and all semiconductor products fail with some probability. It is possible that these probabilistic failures could give rise to accidents or events that could endanger human lives, that could give rise to smoke or fire, or that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor products (including technical data,services) described or contained herein are controlled under any of applicable local export control laws and regulations, such products must not be exported without obtaining the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written permission of SANYO Semiconductor Co., Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO Semiconductor believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties.
This catalog provides information as of September, 2006. Specifications and information herein are subject to change without notice.
PS No.A0503-9/9

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